Field of Invention
This invention relates to an integrated circuit (IC) process, and particularly relates to a patterned material layer with a particular boundary layout structure, and a patterning method for defining patterns of the above patterned material layer on a substrate.
Description of Related Art
As the pitch of patterns in IC process becomes smaller, the lithography illumination mode needs a very strong off-axis illumination (OAI). Meanwhile, defining an array of hole or pillar patterns is a challenge for the lithography process, especially when the pitch of the patterns is near the exposure tool limitation (k1<0.3).
The challenge exists not only because the array is dense, but also because the transfer of boundary holes or pillars tends to be bad and problems such as blind holes, hole bridging, worse profile, worse critical dimension uniformity (CDU) in the after-development critical dimension (DCD) or the after-etching critical dimension (ECD), and smaller process windows may occur in the lithography process and the etching process.